1. Field of the Invention
The present invention relates to sheet computers, wearable computers, display devices, fabrication methods, and electronic devices thereof, and, more particularly, to improved technologies for implementing multifunctional and high-performance electronic circuits that are fabricated on thin substrata.
2. Description of the Related Art
Liquid crystal displays have come into widespread use in the fields of information and consumer electronics, and so forth. However, the technology known as ‘System-On-Panel’ that is oriented toward further performance increases and cost reductions is still under development. ‘System-On-Panel’ is an integration technology for forming a liquid crystal display and peripheral circuits on the same substratum. In addition to making it possible to implement increased reliability and cost reductions due to shortening the manufacturing and testing processes of the display units, this technology makes it feasible to develop the application products that are of a high density, more multifunctional and more compact than ever before.
As a means of implementing the System-On-Panel, there have been attempts at using the poly-silicon TFT technologies, which perform thin film deposition at lower process temperature of 500° C. or less, in order to form TFT circuits on glass substrata. However, the wiring resistance and the critical path delay of the circuits tends to increase as the feature size of the TFT technology reduces and the chip area increases. In addition, in comparison with single-crystal TFT, the mobility of poly-silicon TFT is lower, and hence the operating speed of the poly-silicon TFT circuits is kept lower, especially in synchronous design where the global clock drives the circuits.
This is because the maximum operating frequency of conventional synchronous circuits with the global clocking is the reciprocal of the total delay of the critical path including design margin of delay against temperature and supply voltage variation. Plus both clock jitter and skew must account for the drawback in the expected operating frequency.
As a means of solving this problem, local clocking has been considered. This technique divides the whole circuit into a plurality of sub-blocks from functional perspective, and supplies dedicated local clocks to each of the sub-blocks. The critical path of sub-block must be substantially shorter than that of the original whole circuit. While each of the sub-blocks is constituted as a synchronous circuit that is synchronously driven by the local dock, each sub-block connects the other asynchronously. That is, although the circuit as a whole operates asynchronously, locally, the circuits operate synchronously. By a means of reducing the delay of the critical path, the performance of the whole circuit can be greatly improved.
As patent publications that make reference to local clocking, Japanese Patent Publication No. 2001-516926, Japanese Patent Application Laid Open No. 2001-326826, and Japanese Patent Application Laid Open No. 2002-14914, and so forth, are known, for example. Further, Japanese Patent Publication No. 2002-523857, or the like, is known as a patent that refers to reusing synchronous circuit blocks as IPs by asynchronously connecting them as a whole.
However, because the phase of the local clocks differs for each sub-block, the process of designing a circuit in which sub-blocks operating in local clocks are asynchronously connected is extremely complex and difficult in order to form a high-performance large-scale circuit on a glass substratum as a System-On-Panel, the development of new design technique that makes it possible to disregard the dock skew is desirable. In addition, because the amount of power dynamically consumed in conventional synchronous circuit driven by a global clock is large, circuit design technique implementing low power consumption is required.